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| PRELIMINARY DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR ICS871004I-04 GENERAL DESCRIPTION The ICS871004I-04 is a high perfor mance IC S Differential-to-0.7V Differential Jitter Attenuator HiPerClockSTM designed for use in PCI ExpressTM systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, highphase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS871004I-04 has 3 PLL bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The ICS871004I04 can be set for different modes using the F_SEL pins as shown in Table 3C. The ICS871004I-04 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express addin cards. Features * Four 0.7V differential output pairs * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 640MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 19ps (typical) * Additive phase jitter, RMS: 0.23ps (typical) * 3.3V operating supply * Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages PLL BANDWIDTH BW_SEL[1:0] 0 0 = PLL Bandwidth: ~200kHz 0 1 = PLL Bandwidth: ~400kHz (default) 1 0 = PLL Bandwidth: ~800kHz 1 1 = PLL BYPASS BLOCK DIAGRAM IREF + Pullup PIN ASSIGNMENT nQ0 nQ2 Q2 VDD IREF GND MR BW_SEL0 VDDA F_SEL0 VDD OE 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q0 VDD Q1 nQ1 Q3 nQ3 BW_SEL1 F_SEL1 GND GND nCLK CLK OE F_SEL[1:0] Pulldown BW_SEL[1:0] Pulldown:Pullup 2 2 Control Logic Q0 nQ0 CLK Pulldown nCLK Pullup Phase Detector VCO 490 - 640MHz M U X 0 0 /5 (default) Q1 nQ1 0 1 /4 1 0 /2 1 1 /1 Q2 nQ2 ICS871004I-04 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body /5 MR Pulldown Q3 nQ3 G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 1 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number 1, 24 2, 3 4, 11, 23 5 6, 15, 16 7 Name nQ0, Q0 nQ2, Q2 VDD IREF GND MR Type Output Output Power Input Power Input Description Differential output pair. PCI Express interface levels. Differential output pair. PCI Express interface levels. Core supply pin. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode QAx/nQAx and QBx/nQBx clock outputs. Power supply ground. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pullup See Table 3B. Analog supply pin. Frequency select pins. LVCMOS/LVTTL interface levels. Pulldown See Table 3C. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pulldown See Table 3B. Differential output pair. PCI Express interface levels. Differential output pair. PCI Express interface levels. Pullup 8 9 10 , 17 12 13 14 18 19, 20 21, 22 BW_SEL0 VDDA F_SEL0, F_SEL1 OE CLK nCLK BW_SEL1 nQ3, Q3 nQ1, Q1 Input Power Input Input Input Input Input Output Output NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 2 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs OE 0 1 Q0:Q3 HiZ Enabled Outputs nQ0:nQ3 HiZ Enabled TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs BW_SEL1 0 0 1 1 BW_SEL0 0 1 0 1 PLL Bandwidth ~200kHz ~400kHz (default) ~800kHz PLL BYPASS TABLE 3C. FREQUENCY SELECT FUNCTION TABLE Input Frequency 100 100 100 100 Inputs F_SEL1 F_SEL0 0 0 0 1 1 1 0 1 Divider Value 5 4 2 1 Output Frequency Range (MHz) 100 (default) 125 250 500 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 3 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 82.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V10%, TA = -40C TO 85C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD - IDDA*10 Typical 3.3 3.3 TBD TBD Maximum 3.465 VDD Units V V mA mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V10%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage Input Low Voltage Input High Current Input Low Current MR, OE, F_SEL0. F_SEL1, BW_SEL0, BW_SEL1 MR, OE, F_SEL0. F_SEL1, BW_SEL0, BW_SEL1 BW_SEL0, OE MR, BW_SEL1, F_SEL0. F_SEL1 BW_SEL0, OE MR, BW_SEL1, F_SEL0. F_SEL1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum Typical 2 VDD - 0.3 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.3 5 150 Units V V V V A A A A VIL IIH IIL TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V10%, TA = -40C TO 85C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK, CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V -150 0.15 1.3 VDD - 0.85 5 15 0 Minimum Typical Maximum 15 0 Units A A A A V V Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK at VDD + 0.3V. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 4 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V10%, TA = -40C TO 85C Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section Cycle-to-Cycle Jitter ; NOTE 2 PLL Lock Time Voltage High Voltage Low Max. Voltage, Overshoot Min. Voltage, Undershoot Ringback Voltage Absolute Crossing Voltage Total Variation of VCROSS over all edges Output Rise/Fall Time Rise/Fall Time Variation Rise/Fall Matching Output Duty Cycle 50 measured between 0.175 to 0.525 475 125 125 250 -0.3 0.2 550 140 660 -150 VHIGH + 0.3 PLL in BYPASS Mode PLL in BYPASS Mode 100MHz, Integration Range: 12kHz - 20MHz PLL Mode Test Conditions Minimum 98 3.8 0.23 19 TBD 850 Typical Maximum 640 Units MHz ns ps ps ms mV mV V V V mV mV ps ps ps % tjit tjit(cc) tL VHIGH VLOW VOVS VUDS Vrb VCROSS VCROSS tR / tF tR /tF tRFM odc NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 5 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 100MHz (12kHz to 20MHz) = 0.23ps typical SSB PHASE NOISE dBc/HZ OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 6 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD VDD VDDA 49.9 33 100 Measurement Point nCLK V PP HSCL 33 GND 475 49.9 100 2pF Measurement Point Cross Points V CMR CLK GND 2pF 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT - TBD DIFFERENTIAL INPUT LEVEL nQ0:nQ3 Q0:Q3 tcycle n tjit(cc) = tcycle n -tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER SE MEASUREMENT POINTS FOR RISE/FALL TIME MATCHING IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR tcycle n+1 DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD 7 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION, CONTINUED SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK SE MEASUREMENT POINTS FOR DELTA CROSS POINT IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 8 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS871004I04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that V DDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01F VDDA .01F 10F 10 FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. OUTPUTS: DIFFERENTIAL OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 9 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 2.5V 3.3V 2.5V *R3 33 Zo = 50 R3 120 Zo = 60 R4 120 CLK CLK Zo = 50 nCLK Zo = 60 nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input SSTL R1 120 R2 120 HiPerClockS *Optional - R3 and R4 can be 0 FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 10 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY RECOMMENDED TERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50U impedance. FIGURE 4A. RECOMMENDED TERMINATION Figure 6B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50U impedance. FIGURE 4B. RECOMMENDED TERMINATION IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 11 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP JA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 82.3C/W 1 78C/W 2.5 75.9C/W TRANSISTOR COUNT The transistor count for ICS871004I-04 is: 1395 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 12 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 13 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number ICS871004AGI-04 ICS871004AGI-04T ICS871004AGI-04LF ICS871004AGI-04LFT Marking ICS871004AI04 ICS871004AI04 ICS71004AI04L ICS71004AI04L Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 14 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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